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Allwinner /D1H /UART[3] /FCR

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Interpret as FCR

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https://regviz.com/r/Allwinner/D1H/UART[2]/FCR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (fifoe)fifoe 0 (rfifor)rfifor 0 (xfifor)xfifor 0 (mode_0)dmam 0 (empty)tft0 (one_character)rt

tft=empty, rt=one_character, dmam=mode_0

Description

UART FIFO Control Register

Fields

fifoe
rfifor
xfifor
dmam

0 (mode_0): undefined

1 (mode_1): undefined
tft

0 (empty): undefined

1 (two_characters): undefined

2 (quarter_full): undefined

3 (half_full): undefined
rt

0 (one_character): undefined

1 (quarter_full): undefined

2 (half_full): undefined

3 (two_less_than_full): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data